The DLX is a reduced instruction set computer (RISC) processor architecture. It is mainly a cleaner, simpler MIPS architecture, with a simple 32-bit load/store design, and intended mainly for education, as are Donald Knuth's MIX and MMIX architectures. All three are widely used in college-level computer architecture courses. DLX was introduced in the textbook "Computer Architecture: A Quantitative Approach", by John L. Hennessy and David A. Patterson, the main designers of the MIPS and Berkeley RISC designs, respectively, which are the two benchmark RISC designs.
  • ASPIDA Project ASynchronous, open source, Processor IP of the DLX Architecture. Goal: show feasibility to design and deliver asynchronous open IPs in portable, re-usable way. Information, downloads. Open source hardware.
  • David R. Kaeli, Professor Director of Northeastern University Computer Architecture Research Laboratory, and co-author of Computer Architecture: A Quantitative Approach. Professional information with some links.
  • DLX CPU in SCMOS Photo with descriptions.
  • DLX Implementation at MSU Documents DLX implementation by Microsystems Prototyping Laboratory (MPL), MSU Engineering Research Center; used as design driver to help validate standard cell libraries.
  • DLX in VHDL VHDL model of processor; most instructions use 5 clock cycles to run, jumps use 3, floating point timing not fully accurate because fp instructions also take 5 cycles to run; description, download.
  • DLX Information Documents: getting started, instruction set summary and description, simulator manual.
  • DLX Instruction Slides Tables of instructions, categorized, as PDF slides. By Guy Even, Tel Aviv University.
  • Implementation of 5-stage DLX Pipeline Introductory tutorial with definitions, explanations, examples to show basic pipelining ideas; applet simulation lets users choose instructions to run, and see how pipeline works from direct experience.
  • Introduction to Operating Systems DLXOS information needed for programming, from introductory course on OSs.
  • Norman Matloff's DLX Tutorial Information on DLX processor simulator and compiler, DLXsim, interactive program, loads assembly programs and simulates operation of computer on them, single-stepping or continuous execution.
  • Out of Order Execution Master's Thesis: Design and Evaluation of a RISC Processor with a Tomasulo Scheduler. Uses DLX. HTML, PS, GZ, PDF.
  • Superscalar DLX Processor Diagram, description, download.
  • The DLX Instruction Set Architecture Handbook By Philip M. Sailer, David R. Kaeli; Morgan Kaufmann, 1996, ISBN 1558603719, 1st edition. Definitive work on DLX instructions. Information and abstract. ACM Portal.
  • The DLX Processor Class overview with tables (instruction format, set) and diagrams (timing), some other information. By Ethan Miller, University of Maryland.
  • Verilog Model for DLX Processor PDF slides, mostly code.
  • Wikipedia: DLX Encyclopedia article with links to many related topics.
  • WinDLX Program for MS Windows, an assembly interpreter for DLX assembly language; instructions, source code, downloads. By Javier Echaiz, National University of the South.

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40 korisnika prisutno: 3 registrovanih, 1 skrivenih i 36 senkica. Ulogovani: cesko, galeksic, niko650 (01:08)

Bolje te vidim kad sklopim oči - Milan Višnjić
Uto 16.12.2014 8:31, micha@Umetnost
Jedan od cudnijih snova
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Iz moje svaštare
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Sanjam stalno bivseg momka. Da li to ista znaci?
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Poezija - najlepsi stihovi
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Filigranska kapija od stihova - Dejan Milenković
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Recepti, jela od mesa - rostiljijada
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